1. Field
Exemplary embodiments of the present invention relate to fabrication technology of a semiconductor device, and more particularly, to a semiconductor memory device having a cell structure suitable for high integration and a method for fabricating the same.
2. Description of the Related Art
A semiconductor device using resistance variation for storing data such as ReRAM (Resistive Random Access Memory) is being developed as a substitute for DRAM and flash memory devices. A semiconductor memory device using resistance variation for data storage may include switching elements and variable resistor elements. Furthermore, the semiconductor memory device includes word lines, bit lines, and source lines which couple the switching elements and the variable resistor elements.
In a conventional semiconductor memory device, planar transistors which have the source and drain regions positioned on a same plane are used as the switching elements. In this case, since a bit line and a source line are to be coupled to planar transistors, a cell size to 6F2 or less is hard to achieve. Accordingly, there is a limit in increasing the integration degree of the semiconductor memory device and reduction in production costs.
When source lines are arranged in parallel to word lines and arranged to cross bit lines, a signal may be transmitted to all memory cells coupled to a word line through one source line. Here, a voltage drop may occur and cause deterioration in interconnection reliability. Thus, operation characteristics of the semiconductor memory device may deteriorate.
To address such features, source lines may be arranged in parallel to bit lines and cross the word lines. In such a case, cell sizes may increase, and additional complexity in the structure of the semiconductor memory device may occur in arranging the source lines within a semiconductor memory device.